18 asic design engineer job offers in Bareilly, Uttar Pradesh

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  • Asic rtl design

    eInfochips Bareilly, Uttar Pradesh  +78 locations

    ASIC RTL Design Engineer/Lead Job Location: BLR, HYD, AHM, NOIDA, CHENNAI Work From Office (No Work from Home) Roles and Responsibilities: 4. 9 years of ASIC...
    14 days ago in Jobrapido

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  • Senior engineer – asic design verification

    eInfochips Bareilly, Uttar Pradesh  +4 locations

    Role: Senior Engineer – ASIC Design Verification Location: Across India Experience: 4 to 8 Years WORK FROM OFFICE: Bangalore | Hyderabad |Chennai |Noida |...
    Gross/year: ₹ 6.90 lakhs
    13 days ago in Labor24

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  • Senior Engineer – ASIC Design Verification

    eInfochips Bareilly, Uttar Pradesh  +78 locations

    Role: Senior Engineer – ASIC Design Verification Location: Across India Experience: 4 to 8 Years WORK FROM OFFICE: Bangalore | Hyderabad |Chennai |Noida |...
    14 days ago in Jobrapido

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  • Senior Engineer – ASIC Verification - Bangalore, Hyderabad...

    eInfochips Bareilly, Uttar Pradesh  +78 locations

    Role: Senior Engineer – ASIC Design Verification Job Location: Bangalore, Hyderabad, Noida, Chennai, Ahmedabad, Pune Experience: 4 to 8 Years (NO WORK FROM...
    14 days ago in Jobrapido

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  • VLSI - Synthesis and Static Timing Analysis - Senior Design...

    Eteros Technologies Bareilly, Uttar Pradesh  +78 locations

    ...ASIC timing constraints generation and timing closure. Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good...
    30+ days ago in Jobrapido

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  • Power-domain implementation (Low-power/IR-Drop/) Engineer

    Eteros Technologies Bareilly, Uttar Pradesh

    ...Tech/M. Tech/PhD with at least 3+ years hands-on experience in ASIC/SOC low-power implementation/Power-analysis/IR Drop analysis/Reliability(EM/ESD)
    10 days ago in Talent.com

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  • Power-domain implementation (Low-power/IR-Drop/) Engineer

    Eteros Technologies Bareilly, Uttar Pradesh  +78 locations

    ...Tech/M. Tech/PhD with at least 3+ years hands-on experience in ASIC/SOC low-power implementation/Power-analysis/IR Drop analysis/Reliability(EM/ESD)
    25 days ago in Jobrapido

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  • Asic rtl design

    eInfochips Bareilly, Uttar Pradesh

    ASIC RTL Design Engineer/Lead Job Location: BLR, HYD, AHM, NOIDA, CHENNAIWork From Office (No Work from Home) Roles and Responsibilities: 4. 9 years of ASIC...
    6 days ago in Whatjobs

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  • Senior Engineer – ASIC Design Verification

    eInfochips Bareilly, Uttar Pradesh

    Role: Senior Engineer – ASIC Design VerificationLocation: Across IndiaExperience: 4 to 8 YearsWORK FROM OFFICE: Bangalore | Hyderabad |Chennai |Noida |...
    7 days ago in Whatjobs

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  • Senior Engineer – ASIC Verification - Bangalore, Hyderabad...

    new eInfochips Bareilly, Uttar Pradesh

    Role: Senior Engineer – ASIC Design VerificationJob Location: Bangalore, Hyderabad, Noida, Chennai, Ahmedabad, PuneExperience: 4 to 8 Years(NO WORK FROM HOME...
    15 h 14 minutes ago in Whatjobs

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  • VLSI - Synthesis and Static Timing Analysis - Senior Design...

    Eteros Technologies Bareilly, Uttar Pradesh

    ...ASIC timing constraints generation and timing closure. • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good...
    6 days ago in Whatjobs

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  • Power-domain implementation (Low-power/IR-Drop/) Engineer

    Eteros Technologies Bareilly, Uttar Pradesh  +77 locations

    ...with at least 3+ years hands-on experience in ASIC/SOC low-power implementation/Power-analysis/IR Drop analysis/Reliability(EM/ESD) Analysis. Experience: •
    6 days ago in Whatjobs

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  • CGQ103 | Senior Engineer – ASIC Design Verification

    eInfochips Bareilly, Uttar Pradesh

    Role: Senior Engineer – ASIC Design Verification Location: Across India Experience: 4 to 8 Years WORK FROM OFFICE: Bangalore | Hyderabad |Chennai |Noida |...
    5 days ago in Kitjob_in

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  • Physical Design Engineer | [GDR-358]

    cadence design systems Bareilly, Uttar Pradesh

    ...design, and computer architecture is desirable Should have excellent communication, analytical and problem solving skills Should be self-motivated and good...
    5 days ago in Kitjob_in

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  • (J-621) RTL Engineer and Design Verification engineer

    TESSOLVE Bareilly, Uttar Pradesh  +2 locations

    > > Opportunity With Tessolve Semiconductor. Bangalore > > > > > Hi All, > > we are hiring RTL design engineer and design...
    2 days ago in Kitjob_in

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  • VLSI - Synthesis and Static Timing Analysis - Senior Design...

    Eteros Technologies Bareilly, Uttar Pradesh

    ...ASIC timing constraints generation and timing closure. Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good...
    5 days ago in Kitjob_in

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  • AMS Verification Engineer | [HA940]

    MediaTek Bareilly, Uttar Pradesh  +1 Location

    Skills/Experience: Quick learner with strong critical thinking and creative problem-solving skills. Solid knowledge in ASIC design process, computer...
    5 days ago in Kitjob_in

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  • (NGE12) | DFT Engineer/Lead/ Manager

    TESSOLVE Bareilly, Uttar Pradesh

    > > Immediate hiring! Gt; > > > > Tessolve Semiconductors is hiring for below positions > > Position: DFT Engineer > >...
    2 days ago in Kitjob_in

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