9 asic design engineer job offers in state of Haryana

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  • Asic Design Verification Engineer (Panchkula)

    new Important Group Panchkula, Haryana

    Role Overview: We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal...
    16 h 38 minutes ago in Kitjob_in

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  • ASIC Design Verification Engineer (Faridabad)

    new Tata Consultancy Services Faridabad, Haryana  +2 locations

    Role Overview: We are looking for Senior ASIC Design Verification Engineers with robust expertise in System Verilog (SV) and UVM methodology. The ideal...
    1 day ago in Kitjob_in

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  • ASIC Design Verification Engineer (Panipat)

    new Tata Consultancy Services Panipat, Haryana

    Role Overview: We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal...
    1 day ago in Kitjob_in

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  • ASIC SOC RTL Design Lead (Architect) (Panchkula)

    new Eximietas Design Panchkula, Haryana

    Hi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber...
    1 day ago in Kitjob_in

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  • ASIC SOC RTL Design Lead (Architect) (Panipat)

    new Eximietas Design Panipat, Haryana  +7 locations

    Hi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber...
    1 day ago in Kitjob_in

    Report

  • ASIC SOC RTL Design Lead (Architect) (Faridabad)

    new Eximietas Design Faridabad, Haryana  +3 locations

    Hi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber...
    1 day ago in Kitjob_in

    Report

  • Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem...

    new Proxelera Panchkula, Haryana  +83 locations

    ...performance modeling, or power/perf analysis skills. Scripting for design productivity (Tcl/Python), used in service of hands-on RTL work. Best, Shahid
    1 day ago in Kitjob_in

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  • Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem...

    new Proxelera Panipat, Haryana  +83 locations

    ...performance modeling, or power/perf analysis skills. Scripting for design productivity (Tcl/Python), used in service of hands-on RTL work. Best, Shahid
    1 day ago in Kitjob_in

    Report

  • Senior/Principal Asic Rtl Design Engineer (Soc/Subsystem...

    new Recognized Faridabad, Haryana  +4 locations

    ...performance modeling, or power/perf analysis skills. Scripting for design productivity (Tcl/Python), used in service of hands-on RTL work. Best, Shahid
    16 h 55 minutes ago in Kitjob_in

    Report
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