1,181 design engineer job offers in state of Maharashtra
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Principal Physical Design Engineer (Low Power PD Expert) |...
Aion Silicon Mumbai, Maharashtra +4 locations
...domain DVFS Memory sleep/LP modes & control thereof Other power-vs-performance techniques (eg. Active body biasing) Low-power design UPF development (including
2 days ago in Kitjob_inReport -
Principal Physical Design Engineer (Low Power PD Expert...
Aion Silicon Thane, Maharashtra +7 locations
We are currently recruiting for a Principal Physical Design Engineer who is an expert in Low Power Design. This role will be based in the office in either...
3 days ago in Kitjob_inReport -
KE552 - Principal Physical Design Engineer (Low Power PD...
Aion Silicon Thane, Maharashtra +9 locations
We are currently recruiting for a Principal Physical Design Engineer who is an expert in Low Power Design. This role will be based in the office in either...
2 days ago in Kitjob_inReport -
Senior Design Engineer (Engineering Products, 5+ yrs, Pune...
Michael Page Pune, Maharashtra
...company. Opportunity to contribute to groundbreaking projects in a fast-paced R&D; setting Job Description. Lead the conceptualization and detailed design...
2 days ago in Kitjob_inReport -
[LCT-405] Principal Physical Design Engineer (Low Power PD...
Aion Silicon Nashik, Maharashtra +24 locations
...domain DVFS Memory sleep/LP modes & control thereof Other power-vs-performance techniques (eg. Active body biasing) Low-power design UPF development (including
2 days ago in Kitjob_inReport -
[OUD-385] Principal Physical Design Engineer (Low Power PD...
Aion Silicon Sangli, Maharashtra +24 locations
...domain DVFS Memory sleep/LP modes & control thereof Other power-vs-performance techniques (eg. Active body biasing) Low-power design UPF development (including
2 days ago in Kitjob_inReport -
ZCH-37 - Principal Physical Design Engineer (Low Power PD...
Aion Silicon Kolhapur, Maharashtra +9 locations
...domain DVFS Memory sleep/LP modes & control thereof Other power-vs-performance techniques (eg. Active body biasing) Low-power design UPF development (including
2 days ago in Kitjob_inReport -
(MTS-488) Principal Physical Design Engineer (Low Power PD...
Aion Silicon Thane, Maharashtra +2 locations
...domain DVFS Memory sleep/LP modes & control thereof Other power-vs-performance techniques (eg. Active body biasing) Low-power design UPF development (including
2 days ago in Kitjob_inReport -
6+yr Senior design verification engineer - 7th June VIRTUAL...
HCLTech Mumbai, Maharashtra +27 locations
5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic)...
2 days ago in Kitjob_inReport -
6+yr Senior design verification engineer - 7th June VIRTUAL...
HCLTech Aurangabad, Maharashtra +27 locations
5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic)...
2 days ago in Kitjob_inReport -
6+yr Senior design verification engineer - 7th June VIRTUAL...
HCLTech Dombivli, Maharashtra +2 locations
5-7 years of experience in design verification for ASICs or SoCs. Strong understanding of digital design principles (combinational logic, sequential logic)...
3 days ago in Kitjob_inReport -
SOC Design Verification Engineer (Onsite in Malaysia...
Abhidi Solution Thane, Maharashtra +17 locations
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
2 days ago in Kitjob_inReport -
SOC Design Verification Engineer (Onsite in Malaysia) |...
Abhidi Solution Nagpur, Maharashtra
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
2 days ago in Kitjob_inReport -
Soc Design Verification Engineer Onsite In Malaysia...
new Abhidi Solution Dombivli, Maharashtra +2 locations
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
1 day ago in Kitjob_inReport -
Soc Design Verification Engineer Onsite In Malaysia...
new Abhidi Solution Navi Mumbai, Maharashtra +1 Location
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
1 day ago in Kitjob_inReport -
[ZA443] - 6+yr Senior design verification engineer - 7th...
HCLTech Nagpur, Maharashtra +15 locations
5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic)...
2 days ago in Kitjob_inReport -
(GRH896) | 6+yr Senior design verification engineer - 7th...
HCLTech Pune, Maharashtra +6 locations
5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic)...
3 days ago in Kitjob_inReport -
[UW-596] SOC Design Verification Engineer (Onsite in...
Abhidi Solution Amravati, Maharashtra +3 locations
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
3 days ago in Kitjob_inReport -
(QGP-853) - Soc Design Verification Engineer Onsite In...
new Abhidi Solution Nashik, Maharashtra +2 locations
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
1 day ago in Kitjob_inReport -
CNN-058 Soc Design Verification Engineer Onsite In Malaysia...
new Abhidi Solution Thane, Maharashtra +4 locations
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
1 day ago in Kitjob_inReport -
(D-184) | Soc Design Verification Engineer Onsite In...
new Abhidi Solution Kolhapur, Maharashtra +4 locations
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
1 day ago in Kitjob_inReport -
VF-486 - SOC Design Verification Engineer (Onsite in...
Abhidi Solution Solapur, Maharashtra +11 locations
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
2 days ago in Kitjob_inReport -
[GE-344] Soc Design Verification Engineer Onsite In...
new Abhidi Solution Nagpur, Maharashtra +1 Location
...SV/UVM Knowledge. KEY RESPONSIBILITIES: IOHUB Subsystem test plan creation, DRVR implementation and verification closure. Closely work with Design/Architecture...
1 day ago in Kitjob_inReport -
[BEP500] - Senior Verification Specialist Functional Design...
new Important Group Amravati, Maharashtra
...of a dynamic, supportive team where you can grow your technical expertise and leadership capabilities, while helping shape the future of semiconductor design.
1 day ago in Kitjob_inReport -
6+yr Senior design verification engineer - 7th June VIRTUAL...
HCLTech Sangli, Maharashtra +27 locations
5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic)...
2 days ago in Kitjob_inReport
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