Drive test engineer job offers in maharashtra
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Sr Principal ASIC Vefication Engineer(UCIe PHY IP...
Cadence System Design and Analysis Amravati, Maharashtra +7 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Mumbai...
Cadence System Design and Analysis Mumbai, Maharashtra +7 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP...
Cadence System Design and Analysis Dombivli, Maharashtra +7 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Sangli...
Cadence System Design and Analysis Sangli, Maharashtra +7 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Nagpur
new Cadence System Design and Analysis Nagpur, Maharashtra +9 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Solapur
new Cadence System Design and Analysis Solapur, Maharashtra +9 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Kolhapur
new Cadence System Design and Analysis Kolhapur, Maharashtra +9 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Nashik...
Cadence System Design and Analysis Nashik, Maharashtra +6 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Navi...
Cadence System Design and Analysis Navi Mumbai, Maharashtra
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Amravati
new Cadence System Design and Analysis Amravati, Maharashtra +4 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Navi...
new Cadence System Design and Analysis Navi Mumbai, Maharashtra +1 Location
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Mumbai
new Cadence System Design and Analysis Mumbai, Maharashtra +1 Location
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP...
Cadence System Design and Analysis Aurangabad, Maharashtra +4 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip...
new Cadence System Design and Analysis Aurangabad, Maharashtra +31 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Sangli
new Cadence System Design and Analysis Sangli, Maharashtra +31 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Thane
new Cadence System Design and Analysis Thane, Maharashtra +31 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Pune
new Cadence System Design and Analysis Pune, Maharashtra +31 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Mumbai...
Cadence System Design and Analysis Mumbai, Maharashtra +57 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Nagpur...
Cadence System Design and Analysis Nagpur, Maharashtra +57 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Thane)
Cadence System Design and Analysis Thane, Maharashtra +57 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Pune)
Cadence System Design and Analysis Pune, Maharashtra +57 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP...
Cadence System Design and Analysis Kolhapur, Maharashtra +13 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP...
Cadence System Design and Analysis Solapur, Maharashtra +13 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Senior Software Engineer - Automation Testing & Java Coding...
MasterCard Pune, Maharashtra
...test plans and schedules. 2) Support the team in release/iteration planning and the design of user stories and acceptance criteria. 3) Undertake Requirements
4 days ago in Kitjob_inReport -
Senior Staff Engineer Software -automation & Devops (Pune)
Palo Alto Networks Pune, Maharashtra
...test and deployment strategies identifying bottlenecks and introducing innovative automation solutions to enhance efficiency reliability and developer...
3 days ago in Kitjob_inReport
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