Fpga engineer job offers in gujarat
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Sr. ASIC Design Verification Engineer – TB Architecture...
Proxelera Vapi, Gujarat +33 locations
Hi. We are looking for a senior ASIC Design Verification engineer who owns testbench architecture, not just tests. This role is about building scalable UVM...
4 days ago in Kitjob_inReport -
Sr. ASIC Design Verification Engineer – TB Architecture...
Proxelera Gandhinagar, Gujarat
Hi. We are looking for a senior ASIC Design Verification engineer who owns testbench architecture, not just tests. This role is about building scalable UVM...
4 days ago in Kitjob_inReport -
Senior SoC Director (Bhavnagar)
Omni Design Technologies Bhavnagar, Gujarat +1 Location
...timing analysis in Cadence / Synopsys design environments. Directed and constrained random verification, UVM methodology. Embedded systems FPGA emulation,
2 days ago in Kitjob_inReport -
Senior SoC Director (Jamnagar)
Omni Design Technologies Jamnagar, Gujarat +1 Location
...timing analysis in Cadence / Synopsys design environments. Directed and constrained random verification, UVM methodology. Embedded systems FPGA emulation,
2 days ago in Kitjob_inReport -
Senior SoC Director (Anand)
Omni Design Technologies Anand, Gujarat
...timing analysis in Cadence / Synopsys design environments. Directed and constrained random verification, UVM methodology. Embedded systems FPGA emulation,
2 days ago in Kitjob_inReport -
Senior SoC Director (Rajkot)
Omni Design Technologies Rajkot, Gujarat
...timing analysis in Cadence / Synopsys design environments. Directed and constrained random verification, UVM methodology. Embedded systems FPGA emulation,
2 days ago in Kitjob_inReport -
Senior SoC Director (Gandhinagar)
Omni Design Technologies Gandhinagar, Gujarat
...timing analysis in Cadence / Synopsys design environments. Directed and constrained random verification, UVM methodology. Embedded systems FPGA emulation,
2 days ago in Kitjob_inReport -
Senior SoC Director (Junagadh)
Omni Design Technologies Junagadh, Gujarat
...power analysis, timing analysis in Cadence / Synopsys design environments. Directed and constrained random verification, UVM methodology. Embedded systems FPGA
2 days ago in Kitjob_inReport
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