Rtl design job offers in hyderabad, andhra pradesh
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Wireless R&D IP Design Staff/Sr Staff (Hyderabad)
new qualcomm Hyderabad, Andhra Pradesh
...Wireless IP development covering WAN, WLAN, GNSS, and Bluetooth technologies. Define and develop next-generation Wireless R&D; products. Work on front-end RTL...
1 day ago in Kitjob_inReport -
Staff ASIC IP/Block/Subsystem Design Verification Engineer...
Micron Hyderabad, Andhra Pradesh
...IP. Should be expert in System Verilog and UVM methodology. Domain: IP/Block/Subsystem Verification (RTL Front end verification) Location: Hyderabad, Bengaluru
2 days ago in Kitjob_inReport -
Electrical Architect (Hyderabad)
Eximietas Design Hyderabad, Andhra Pradesh
...resume to: &#; Referrals are highly appreciated. Best regards, Maruthy Prasaad Associate VLSI Manager. Talent Acquisition | Visakhapatnam Eximietas Design.
5 days ago in Kitjob_inReport -
Architect (Part Time) (Hyderabad)
Eximietas Design Hyderabad, Andhra Pradesh
...resume to: &#; Referrals are highly appreciated. Best regards, Maruthy Prasaad Associate VLSI Manager. Talent Acquisition | Visakhapatnam Eximietas Design.
5 days ago in Kitjob_inReport -
Field-Programmable Gate Arrays Engineer (Hyderabad)
ACL Digital Hyderabad, Andhra Pradesh
RTL FPGA Design Engineers Experience: 1-3 years Location: Hyderabad Expertise RTL Coding in Verilog, System Verilog or VHDL. Robust understanding of FPGA...
3 days ago in Kitjob_inReport -
Senior Lead Secunderabad
new TESSOLVE Secunderabad, Hyderabad, Andhra Pradesh
Physical Design / Location: Bangalore/Coimbatore Typical Qualification B. E/B.Tech/M. Tech in ECE/EEE Solid timing fundamentals 4+years' experience PD –...
1 day ago in Kitjob_inReport -
Senior Lead Hyderabad
new TESSOLVE Hyderabad, Andhra Pradesh
Physical Design / Location: Bangalore/Coimbatore Typical Qualification B. E/B.Tech/M. Tech in ECE/EEE Solid timing fundamentals 4+years' experience PD –...
1 day ago in Kitjob_inReport -
Senior Asic Lead Designer (Hyderabad)
Anonymous Hyderabad, Andhra Pradesh
Job Title: *. Senior ASIC Engineer Design and deliver standards-compliant, production-ready IP blocks for DDR5, HBM4, and LPDDR6 memory controllers. Develop...
3 days ago in Kitjob_inReport -
IP Verification Engineer (Hyderabad)
BITSILICA Hyderabad, Andhra Pradesh
...netlist, isolating issues in both module and system level. Explicit understanding of ASIC design flow. Solid analytical, synthesis and problem solving skills
4 days ago in Kitjob_inReport -
Lead DFT Engineer (Secunderabad)
Silicon Patterns Secunderabad, Hyderabad, Andhra Pradesh
...DFT Engineer Location: Bengaluru, India Experience: 6–10 Years Role Type: Full-time | Silicon Engineering About the Role We are seeking a Lead Design-for-Test...
3 days ago in Kitjob_inReport -
Lead DFT Engineer (Hyderabad)
Silicon Patterns Hyderabad, Andhra Pradesh
...DFT Engineer Location: Bengaluru, India Experience: 6–10 Years Role Type: Full-time | Silicon Engineering About the Role We are seeking a Lead Design-for-Test...
3 days ago in Kitjob_inReport -
Senior / Lead Dft Engineer Secunderabad
Silicon Patterns Secunderabad, Hyderabad, Andhra Pradesh
...DFT Engineer Location: Bengaluru, India Experience: 3–12 Years Role Type: Full time | Silicon Engineering About the Role We are seeking a Lead Design-for-Test...
3 days ago in Kitjob_inReport -
Senior / Lead Dft Engineer Hyderabad
Silicon Patterns Hyderabad, Andhra Pradesh
...DFT Engineer Location: Bengaluru, India Experience: 3–12 Years Role Type: Full time | Silicon Engineering About the Role We are seeking a Lead Design-for-Test...
3 days ago in Kitjob_inReport -
Senior DFT Architect (Hyderabad)
Eximietas Design Hyderabad, Andhra Pradesh
...feel free to forward this within your network. Best regards, Maruthy Prasaad Associate VLSI Manager. Talent Acquisition | Visakhapatnam Eximietas Design.
4 days ago in Kitjob_inReport -
Principal STA /Synthesis Engineer (Hyderabad)
Cadence Hyderabad, Andhra Pradesh
...design teams Apply: Send your updated profile to Equal Opportunity Statement If you are enthusiastic about timing analysis and eager to contribute to...
3 days ago in Kitjob_inReport -
Application Engineering, Staff Engineer (Hyderabad)
new Synopsys Hyderabad, Andhra Pradesh
Alternate Job Titles: Senior Physical Design Application Engineer. Implementation AE – RTL to GDS. EDA Solutions Engineer – Physical Implementation...
13 h 48 minutes ago in Kitjob_inReport -
PD engineer (Hyderabad)
Mirafra Technologies Hyderabad, Andhra Pradesh
...for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.
2 days ago in Kitjob_inReport -
Tolerance Lead Engineer (Contract) (Hyderabad)
ACL Digital Hyderabad, Andhra Pradesh
...with a focus on digital design, DFT or test methodologies is desired. Tessent Scan, ATPG or MBIST certifications are a plus. Apply here or share cvs to
5 days ago in Kitjob_inReport -
Foundation Lead Engineer (Hyderabad)
ACL Digital Hyderabad, Andhra Pradesh
...with a focus on digital design, DFT or test methodologies is desired. Tessent Scan, ATPG or MBIST certifications are a plus. Apply here or share cvs to
5 days ago in Kitjob_inReport -
Lead Engineer - Field Quality (Hyderabad)
ACL Digital Hyderabad, Andhra Pradesh
...with a focus on digital design, DFT or test methodologies is desired. Tessent Scan, ATPG or MBIST certifications are a plus. Apply here or share cvs to
5 days ago in Kitjob_inReport -
Lead Engineer Secunderabad
ACL Digital Secunderabad, Hyderabad, Andhra Pradesh
...with a focus on digital design, DFT or test methodologies is desired. Tessent Scan, ATPG or MBIST certifications are a plus. Apply here or share cvs to
3 days ago in Kitjob_inReport -
Verification Lead (Secunderabad)
ACL Digital Secunderabad, Hyderabad, Andhra Pradesh
Lead – Design Verification (ODC Head – AI SoC Programs) Experience: 14 – 26 Years Location: Bangalore – IBC Knowledge Park, Bannerghatta Road Notice Period...
5 days ago in Kitjob_inReport -
Principal CAD Engineer (Hyderabad)
Renesas Hyderabad, Andhra Pradesh
Principal CAD Engineer Job Description + Own and evolve a defined portion of the Digital RTL‑to‑GDSII CAD/EDA solution, including methodology, automation...
3 days ago in Kitjob_inReport -
Sr Principal ASIC Vefication Engineer(UCIe PHY IP) (Hyderaba
Cadence System Design and Analysis Hyderabad, Andhra Pradesh +9 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
3 days ago in Kitjob_inReport -
Sr Principal Asic Vefication Engineer Ucie Phy Ip Hyderabad
new Cadence System Design and Analysis Hyderabad, Andhra Pradesh +6 locations
Key Responsibilities: Lead DesignVerification (DV) execution of UCIe PHY IP. Drive internal DV team meeting for day to day execution. Work closely with RTL...
1 day ago in Kitjob_inReport
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