Verification engineer job offers in haryana
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Staff embedded software qa engineer
ChargePoint Gurugram, Haryana
...verification Report defects and follow-through as necessary to complete the testing cycle Provide timely status updates and assist the team in making...
5 days ago in Labor24Report -
Storage engineer
Coforge Gurugram, Haryana
Role: Storage & Backup Engineer Location: Gurugram Work Schedule: Work from Office (Hybrid) Immediate Joiners Only We at Coforge are looking for Storage and...
12 days ago in Labor24Report -
Senior Design Verification Engineer
new eInfochips Panipat, Haryana
...in developing verification environment and regression setupCoverage analysis and closureInterested candidates share resume at ----------@einfochips.com
22 h 50 minutes ago in WhatjobsReport -
Senior Design Verification Engineer
eInfochips Faridabad, Haryana
...in developing verification environment and regression setup Coverage analysis and closure Interested candidates share resume at ----------@einfochips.com
5 days ago in WhatjobsReport -
Senior Design Verification Engineer
new eInfochips Raipur, Haryana +87 locations
...in developing verification environment and regression setupCoverage analysis and closureInterested candidates share resume at ----------@einfochips.com
22 h 50 minutes ago in WhatjobsReport -
Senior Design Verification Engineer
new eInfochips Panipat, Haryana +19 locations
...in developing verification environment and regression setupCoverage analysis and closureInterested candidates share resume at ----------@einfochips.com
13 h 33 minutes ago in Talent.comReport -
Senior Design Verification Engineer
new eInfochips Gurgaon, Haryana +87 locations
...in developing verification environment and regression setupCoverage analysis and closureInterested candidates share resume at ----------@einfochips.com
22 h 50 minutes ago in WhatjobsReport -
Senior Design Verification Engineer
CYIENT Raipur, Haryana
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
4 days ago in JobrapidoReport -
Senior Design Verification Engineer
eInfochips Panchkula, Haryana +87 locations
...in developing verification environment and regression setup Coverage analysis and closure Interested candidates share resume at ----------@einfochips.com
6 days ago in WhatjobsReport -
Senior Design Verification Engineer
new eInfochips Faridabad, Haryana +19 locations
...in developing verification environment and regression setupCoverage analysis and closureInterested candidates share resume at ----------@einfochips.com
14 h 12 minutes ago in Talent.comReport -
Senior Design Verification Engineer
CYIENT Faridabad, Haryana
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
4 days ago in JobrapidoReport -
Senior Design Verification Engineer
CYIENT Panipat, Haryana
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
4 days ago in JobrapidoReport -
Senior Design Verification Engineer
CYIENT Gurgaon, Haryana
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
4 days ago in JobrapidoReport -
Senior Design Verification Engineer
CYIENT Panipat, Haryana +81 locations
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
2 days ago in WhatjobsReport -
Senior Design Verification Engineer
CYIENT Raipur, Haryana +81 locations
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
2 days ago in WhatjobsReport -
Emulation Engineer
new ACL Digital Panchkula, Haryana +16 locations
Good understanding of verification and validation fundamentals... Solid understanding of emulation technologies... Should be able to do emulation builds and...
13 h 35 minutes ago in Talent.comReport -
Senior Design Verification Engineer
CYIENT Gurgaon, Haryana +81 locations
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
2 days ago in WhatjobsReport -
Senior Design Verification Engineer
CYIENT Faridabad, Haryana +81 locations
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
2 days ago in WhatjobsReport -
Senior Design Verification Engineer
CYIENT Panchkula, Haryana
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
4 days ago in JobrapidoReport -
Senior Design Verification Engineer
CYIENT Panchkula, Haryana +81 locations
...of verification methodology, assertion-based testing Note: SoC-level DV experience alone is not sufficient Must currently be working on core-level verification
2 days ago in WhatjobsReport -
Verification lead design Engineer
new cadence design systems Panipat, Haryana
...and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
1 day ago in JobrapidoReport -
CAD Engineer
new Canvendor Panipat, Haryana
We are hiring for CAD Engineer, for Bangalore/HyderabadKey Responsibilities: Develop and maintain CAD flows for ASIC design using Design Compiler (DC) and...
14 h ago in Talent.comReport -
Verification lead design Engineer
new cadence design systems Raipur, Haryana +97 locations
...and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
1 day ago in WhatjobsReport -
Verification lead design Engineer
new cadence design systems Gurgaon, Haryana +97 locations
...and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
1 day ago in WhatjobsReport -
Verification lead design Engineer
new cadence design systems Gurgaon, Haryana
...and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
1 day ago in JobrapidoReport
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