Vhdl verilog manager job offers in bangalore, karnataka
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Senior Engineer / Lead Engineer - FPGA
tejas networks Bangalore, Karnataka
Requirement: Reports to: Manager / Senior Manager. FPGA Experience: 3-10 Years Roles and Responsibilities: You will be engaged in end-to-end system...
7 days ago in Talent.comReport -
Staff / Principal Engineer - FPGA
tejas networks Bangalore, Karnataka
Requirement: Reports to: General Manager / Associate VP Experience: 10 – 18 Years Roles and Responsibilities: You will be engaged in end-to-end system...
7 days ago in Talent.comReport -
Advisory Hardware Developer - Power Management
Confidential Bangalore, Karnataka
...and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.
3 days ago in Monster India PREMIUMReport -
Senior Manager FPGA IP & System Design
Confidential Bangalore, Karnataka
...serial bus data. Must have experience in Verilog and/or VHDL coding. Must have very good understanding of physical layer of SERDES of XILINX-AMD or Intel FPGA.
30+ days ago in Monster India PREMIUMReport -
Design Engineering Architech
Confidential Bangalore, Karnataka
...Development Education UG: Any Graduate PG: Any Postgraduate Key Skills Design engineering Automation VHDL DFT Verilog Manager Technology System verilog RTL
Gross/year: ₹ 11 lakhs
30+ days ago in MonsterReport -
Junior Sales Executive
Confidential Bangalore, Karnataka
...Verilog/VHDL, FPGA, ASIC/SoC design). Strong communication, presentation, and interpersonal skills. Ability to travel locally and regionally to visit...
18 days ago in Monster India PREMIUMReport -
Senior Principal Engineer - Physical Design
Confidential Bangalore, Karnataka
...Verilog/VHDL is advantageous. Strong interpersonal skills and the ability to work effectively in a collaborative team environment. In-depth expertise with...
30+ days ago in MonsterReport -
(A-909) | RTL Design Lead
L&T Technology Services Bangalore, Karnataka
RTL Design Engineer with 8+ to 15 of Hands on experiences. Experience/proficiency in RTL design(Verilog/VHDL) architecture implementation using (coding in)...
2 days ago in Kitjob_inReport
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