Vlsi design engineer job offers in delhi
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VLSI - Physical Design Lead Engineer
Eteros Technologies Delhi, Delhi
...design process from RTL->GDS2 • Analog/Mixed/Custom Signal PNR experience preferred to help drive partitioning for digital and mixed signal SoCs •...
10 days ago in Talent.comReport -
VLSI - Physical Design Principal/Staff Engineer
Eteros Technologies Delhi, Delhi
...design process from RTL->GDS2 • Analog/Mixed/Custom Signal PNR experience preferred to help drive partitioning for digital and mixed signal SoCs •...
10 days ago in Talent.comReport -
VLSI - DFT Senior Engineer/Lead Engineer
Eteros Technologies Delhi, Delhi
...SCAN, BIST • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to generate and
10 days ago in Talent.comReport -
Senior Engineer – ASIC Verification - Bangalore, Hyderabad...
eInfochips Delhi, Delhi
Role: Senior Engineer – ASIC Design Verification Job Location: Bangalore, Hyderabad, Noida, Chennai, Ahmedabad, Pune Experience: 4 to 8 Years ABOUT...
30+ days ago in Talent.comReport -
Functional Verification- C/VHDL/Verilog (4-8 yrs...
Infinity HR Consulting Services Noida, Delhi, Delhi
...Product based Organization Job Title: SOC Functional Verifcation Job Location: Greater-Noida Exp: 4 to 8yrs Job Title: SoC Functional Verification Engineer...
20 days ago in HiristReport -
Lead Embedded Software Engineer - Embedded C/+ (6-12 yrs...
Core Gurgaon, Delhi, Delhi
Job Description: The incumbent will be responsible for developing software in custom camera security solutions. Design, develop, and maintain board support...
10 days ago in HiristReport -
VLSI - Physical Design Lead Engineer [PH-308]
Eteros Technologies Delhi, Delhi
...design process from RTL->GDS2• Analog/Mixed/Custom Signal PNR experience preferred to help drive partitioning for digital and mixed signal SoCs•...
3 days ago in Kitjob_inReport -
VLSI - Synthesis and Static Timing Analysis - Senior Design...
Eteros Technologies Delhi, Delhi
...design timing closure flow and methodology. • BTech/MTech/PhD with at least 4+ years hands-on experience in ASIC timing constraints generation and timing...
3 days ago in Kitjob_inReport -
CR-645 Design Verification Engineer
Eximietas Design Delhi, Delhi
About Us: Eximietas Design is a leading technology firm specializing in [VLSI/Cloud Computing/Cyber Security/AI/ML] solutions. With a commitment to...
5 days ago in Kitjob_inReport -
Senior Principal Engineer AMS Circuit design - TOL162
cadence design systems Delhi, Delhi
Senior Principal Engineer AMS Circuit design: Contribute to AMS design for High-speed Memory PHYs. Responsible for entire PHY design or major design...
7 days ago in Kitjob_inReport -
(YA-095) | Node. Js Lead Engineer
Simelabs - Digital AI Metaverse Robotics VLSI Delhi, Delhi
...code concepts Ability to design and architect cloud applications Preferred knowledge in OAuth, SAML, and other security and authentication related concepts
6 days ago in Kitjob_inReport
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