Vlsi design job offers in mumbai, maharashtra

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  • Vlsi- dft- atpg lead

    new HCLTech Mumbai, Maharashtra  +108 locations

    ...of DFT methodologies and the ability to independently implement and optimize DFT strategies. You will be responsible for collaborating with design...
    16 h 37 minutes ago in Talent.com

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  • RTL Design Engineer

    new Quess Corp Mumbai, Maharashtra  +107 locations

    Job Title: RTL Design Engineer Work Location: Hyderabad Experience: 5 Years Notice Period: Immediate (15 Days Max) RTL Quality Check Perform RTL quality...
    1 day ago in Talent.com

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  • Chip Lead

    new SiliconAuto India Mumbai, Maharashtra  +107 locations

    ...(STA) and power-performance-area (PPA) optimization UPF/CPF for low-power design Familiarity with design for manufacturability, test (DFT), and silicon debug.
    1 day ago in Talent.com

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  • AI ML Engineer

    new MaximaTek Mumbai, Maharashtra  +107 locations

    ...Design Engineer SAP Analyst Supply Chain Analyst Clinical Informatics Specialist What We Offer Targeted Placement: Strategic, high-volume promotion of your...
    10 h 52 minutes ago in Talent.com

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  • Vlsi- dft- atpg lead

    new HCLTech Mumbai, Maharashtra  +105 locations

    ...of DFT methodologies and the ability to independently implement and optimize DFT strategies. You will be responsible for collaborating with design...
    20 h 28 minutes ago in Whatjobs

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  • Vlsi- dft- atpg lead

    HCLTech Mumbai, Maharashtra

    ...of DFT methodologies and the ability to independently implement and optimize DFT strategies. You will be responsible for collaborating with design...
    30+ days ago in Jobrapido

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  • Lead DFT Engineer

    new ACL Digital Mumbai, Maharashtra  +108 locations

    Job Title: Lead DFT Engineer Experience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC Design Job Summary: We...
    1 day ago in Talent.com

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  • Staff ASIC Engineer

    new ScaleFlux Mumbai, Maharashtra  +107 locations

    ...design teams to ensure power goals are met Perform power analysis at RTL, gate-level, and post-layout stages Optimize clock gating, power gating, DVFS, and...
    1 day ago in Talent.com

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  • RTL Design Engineer

    Quess Corp Mumbai, Maharashtra

    Job Title: RTL Design Engineer Work Location: Hyderabad Experience: 5 Years Notice Period: Immediate (15 Days Max) RTL Quality Check Perform RTL quality...
    3 days ago in Jobrapido

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  • RTL Design Engineer

    new Quess Corp Mumbai, Maharashtra  +106 locations

    Job Title: RTL Design EngineerWork Location: HyderabadExperience: 5 YearsNotice Period: Immediate (15 Days Max) RTL Quality CheckPerform RTL quality checks...
    1 day ago in Whatjobs

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  • Chip Lead

    SiliconAuto India Mumbai, Maharashtra

    ...(STA) and power-performance-area (PPA) optimization UPF/CPF for low-power design Familiarity with design for manufacturability, test (DFT), and silicon debug.
    3 days ago in Jobrapido

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  • Chip Lead

    new SiliconAuto India Mumbai, Maharashtra  +80 locations

    ...(STA) and power-performance-area (PPA) optimizationUPF/CPF for low-power designFamiliarity with design for manufacturability, test (DFT), and silicon debug.
    1 day ago in Whatjobs

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  • Lead DFT Engineer

    ACL Digital Mumbai, Maharashtra  +105 locations

    ...design, STA, and synthesis flows. Proficient in scripting languages (Python, Perl, Tcl) for flow automation. Deep understanding of silicon test challenges...
    4 days ago in Whatjobs

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  • Electrical Engineering - AI Data Trainer

    Confidential Mumbai, Maharashtra

    ...AI Data Trainer Type: Hourly Contract Compensation: $35–$60 /hour Location: Remote Commitment: 10–40 hours/week What You'll Do Develop Complex Problems: Design...
    7 days ago in Monster

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  • Staff ASIC Engineer

    ScaleFlux Mumbai, Maharashtra

    ...design teams to ensure power goals are met Perform power analysis at RTL, gate-level, and post-layout stages Optimize clock gating, power gating, DVFS, and...
    3 days ago in Jobrapido

    Report

  • Electrical Engineering Expert - AI Content Specialist

    Confidential Mumbai, Maharashtra

    ...Specialist Type: Hourly Contract Compensation: $35–$60 /hour Location: Remote Commitment: 10–40 hours/week What You'll Do Develop Complex Problems: Design...
    4 days ago in Monster

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  • Electronics And Computer Science Internship in Mumbai at 1ac

    1accord Mumbai, Maharashtra

    ...is a prominent company that offers all-around solutions for various mechatronics and automation requirements all over India. We use techniques of design...
    25 days ago in Internshala

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  • AI ML Engineer

    MaximaTek Mumbai, Maharashtra

    ...Design Engineer SAP Analyst Supply Chain Analyst Clinical Informatics Specialist What We Offer Targeted Placement: Strategic, high-volume promotion of your...
    20 days ago in Jobrapido

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  • Lead DFT Engineer

    ACL Digital Mumbai, Maharashtra

    Job Title: Lead DFT Engineer Experience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC Design Job Summary: We...
    30+ days ago in Jobrapido

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  • RTL Design Engineer (Mumbai)

    new Quess Corp Mumbai, Maharashtra

    Job Title: RTL Design Engineer Work Location: Hyderabad Experience: 5 Years Notice Period: Immediate (15 Days Max) RTL Quality Check. Perform RTL quality...
    19 h 36 minutes ago in Kitjob_in

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  • Chip Lead (Mumbai)

    new SiliconAuto India Mumbai, Maharashtra

    ...(STA) and power-performance-area (PPA) optimization UPF/CPF for low-power design Familiarity with design for manufacturability, test (DFT), and silicon debug.
    19 h 20 minutes ago in Kitjob_in

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  • Soc Dft Lead (Mumbai)

    SEMIFIVE Mumbai, Maharashtra

    SoC DFT Lead / DFT Implementation LeadAbout SemifiveFounded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency...
    2 days ago in Kitjob_in

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  • Staff ASIC Engineer (Mumbai)

    new ScaleFlux Mumbai, Maharashtra

    ...design teams to ensure power goals are met. Perform power analysis at RTL, gate-level, and post-layout stages. Optimize clock gating, power gating, DVFS, and
    20 h 14 minutes ago in Kitjob_in

    Report
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