Vlsi design job offers in noida, uttar pradesh
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Vlsi- dft- atpg lead
HCLTech Noida, Uttar Pradesh +108 locations
...of DFT methodologies and the ability to independently implement and optimize DFT strategies. You will be responsible for collaborating with design...
2 days ago in Talent.comReport -
Principal Design Engineer
new cadence design systems Noida, Uttar Pradesh +1 Location
...Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTech/ME/MTech. Electrical / Electronics / VLSI...
15 h 9 minutes ago in Talent.comReport -
Senior Lead STA Engineer
Connectpro Management Consultants Noida, Uttar Pradesh +1 Location
DSP_Senior_Lead_STA_Engineer_Noida. General Summary: As a Senior Lead STA Engineer, you will play a critical role in the design, optimization, verification...
2 days ago in Talent.comReport -
Lead R&D Engineer - SCBU - PowerArtist
new ansys Noida, Uttar Pradesh
...Synopsys, Inc. (Nasdaq: SNPS) accelerates technology innovation from silicon to systems. Catalyzing the era of pervasive intelligence, we deliver design...
15 h ago in Talent.comReport -
Vlsi- dft- atpg lead
HCLTech Noida, Uttar Pradesh +105 locations
...of DFT methodologies and the ability to independently implement and optimize DFT strategies. You will be responsible for collaborating with design...
2 days ago in WhatjobsReport -
Vlsi- dft- atpg lead
HCLTech Noida, Uttar Pradesh
...of DFT methodologies and the ability to independently implement and optimize DFT strategies. You will be responsible for collaborating with design...
30+ days ago in JobrapidoReport -
Lead Design Verification Engineer
Confidential Noida, Uttar Pradesh
Lead Design Verification Engineer – PCIe Gen5/6 Location: Noida, India Experience: 6+ years Role summary Lead Design Verification Engineer with strong...
18 days ago in MonsterReport -
IP Design & Verification Engineer
Confidential Noida, Uttar Pradesh
Looking for Siemens EDA ambassadors: Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies...
11 days ago in MonsterReport -
Senior Lead STA Engineer
Connectpro Management Consultants Noida, Uttar Pradesh
DSP_Senior_Lead_STA_Engineer_Noida. General Summary: As a Senior Lead STA Engineer, you will play a critical role in the design, optimization, verification...
23 days ago in WhatjobsReport -
Analog Layout Engineer -Lead
Confidential Noida, Uttar Pradesh +1 Location
Analog layout design requires knowledge of designing layouts of complex VLSI (very large scale integration) circuits using graphic editing tools in the...
Gross/year: ₹ 14 lakhs
30+ days ago in MonsterReport -
STA/Timing Methodology Engineer (Lead/Staff)
Confidential Noida, Uttar Pradesh
...design flows, methods, and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient...
8 days ago in MonsterReport -
R&d engineer ii - eda
Confidential Noida, Uttar Pradesh
...crucial power and reliability challenges. Driving innovation in emerging 3D IC, FinFET, and stacked-die architectures by addressing critical design closure
30+ days ago in MonsterReport -
Synthesis Lead Engineer
Confidential Noida, Uttar Pradesh
...experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design...
12 days ago in MonsterReport -
RTL Design Engineer (Noida)
Quess Corp Noida, Uttar Pradesh
Job Title: RTL Design Engineer Work Location: Hyderabad Experience: 5 Years Notice Period: Immediate (15 Days Max) RTL Quality Check. Perform RTL quality...
2 days ago in Kitjob_inReport -
Chip Lead (Noida)
SiliconAuto India Noida, Uttar Pradesh
...(STA) and power-performance-area (PPA) optimization UPF/CPF for low-power design Familiarity with design for manufacturability, test (DFT), and silicon debug.
2 days ago in Kitjob_inReport -
Staff ASIC Engineer (Noida)
ScaleFlux Noida, Uttar Pradesh
...and physical design teams to ensure power goals are met. Perform power analysis at RTL, gate-level, and post-layout stages. Optimize clock gating, power
2 days ago in Kitjob_inReport
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